Implementation of transition and coexistence mechanisms for IPV4-IPV6 protocols in computer centers on supported high performance academic networks

Authors

  • Carlos Andrés Martínez Alayón Francisco José de Caldas District University image/svg+xml
  • Roberto Ferro Escobar Francisco José de Caldas District University image/svg+xml
  • Víctor José Arrieta Zambrano Francisco José de Caldas District University image/svg+xml

DOI:

https://doi.org/10.18046/syt.v13i34.2094

Keywords:

IPv6 transition, Dual Stack, tunneling, ISATAP, 6to4, Teredo, SIIT.

Abstract

This document aims to contextualize the reader about some of the mechanisms that currently exist for IPv4-IPv6 transition and evidence some aspects that must be taken into account when evaluating and implementing some of them, specifically in centers of high performance computing and academic networks to support research projects. It also aims to show the implementation and support of IPv6 in e-learning technology platforms.

Author Biographies

  • Carlos Andrés Martínez Alayón, Francisco José de Caldas District University

    Electronic Engineer, Specialist in Network Security. Candidate to Master of Science in Computer Science and Communications. Professor in Telematics, Informatics, and Networks in the Universidad Escuela Colombiana de Carreras Industriales [ECCI] and in the Universidad Distrital Francisco José de Caldas. Coordinator of the Advanced Technology Research Network in the Universidad Distrital [RITA-UD]. Scientific vice-director of the Laboratory of Research and Development in Electronics and Networks [LIDER], also at the Universidad Distrital.

  • Roberto Ferro Escobar, Francisco José de Caldas District University

    Electronic Engineer, Master of Science in Telematics, Informatics, and Networks from the Universidad Distrital Francisco José de Caldas. PhD in Engineering Informatics, Information Society, and Knowledge Management from the Universidad Pontificia de Salamanca. He is currently director of PhD in Engineering program, Dean of Engineering Faculty at the Universidad Distrital Francisco José de Caldas, and associate professor. Director of the Advanced Technology Research Network in the Universidad Distrital [RITA-UD] and scientific director of the Laboratory of Research and Development in Electronics and Networks [LIDER].

  • Víctor José Arrieta Zambrano, Francisco José de Caldas District University

    Electronic Engineer from the Universidad Distrital Francisco José de Caldas. Research assistant at the Laboratory of Research and Development in Electronics and Networks [LIDER]. He has worked in projects related with addressing and routing in IPv4 and IPv6. Network and Support technician at the Advanced Technology Research Network in the Universidad Distrital [RITA-UD].

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Published

2015-09-30

Issue

Vol. 13 No. 34 (2015)

Section

Original Research

License

This journal is licensed under the terms of the CC BY 4.0 licence (https://creativecommons.org/licenses/by/4.0/legalcode).